digital design parallel to serial converter

To know the working of UART, you need to understand the basic functionality of serial communication. Devices like GPS and GSM use slower baud rates in 48. Mostly, microcontrollers come up with higher baud rates such as 11520 for faster data transfer. The baud rate generator generates speeds ranging from 110 bps (bits per second) to 230400. In addition to these, a read or write control logic is provided to tell when to read/write. The transmit shift register and receiver shift register shift the bits to the left or right until a byte of data is sent/received. The Transmit hold register contains the data byte to be transmitted.

The baud rate generator generates the speed at which the transmitter and receiver have to send/receive the data.

It requires a single wire for transmitting the data and another wire for receiving.

It is a cheap communication device with a single transmitter/receiver. When the high-speed data transfer is not required UART is used. Protocols like SPI (serial peripheral interface) and USB (Universal Serial Bus) are used for fast communication. This data is present in modulating form and transmits at a defined baud rate. An 8-bit serial data received from the peripheral device is converted into the parallel form using serial to parallel conversion and parallel data received from the CPU is converted using serial to parallel conversion. The function of UART is to convert the incoming and outgoing data into the serial binary stream. It is a hardware peripheral that is present inside a microcontroller. The I OFF circuitry disables the output, preventing the damaging current backflow through the device when it is powered down.“UART” stands for Universal Asynchronous receiver-transmitter. It is fully specified for partial-power-down applications using I OFF. Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall times. The LOW‑to‑HIGH transition of the input CE should only take place while CP HIGH for predictable operation. The pin assignment for the inputs CP and CE is arbitrary and can be reversed for layout convenience. The clock input is a gate-OR structure which allows one input to be used as an active LOW clock enable input ( CE) input. This feature allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the succeeding stage. It shifts one place to the right (Q0→Q1→Q2, etc.) with each positive-going clock transition. When input PL is HIGH, data enters the register serially at the input DS. When the parallel-load input ( PL) is LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously. The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage.

Digital design parallel to serial converter